ARM Architecture

Automating Knowledge Coherency and Efficiency Testing of Excessive-Velocity SoCs with CXL Interfaces

2023 is right here, and know-how traits round Compute Specific Hyperlink (CXL) and the subsequent era of AMBA protocols (CHI-E/F) are getting extra traction. The most important problem of as we speak is the complexity of dealing with monumental knowledge stream proudly owning to AI, ML, and deep studying functions. To maintain up with the tempo, new era interfaces introduce specialised semantics catering to reminiscence disaggregation, cache consistency, strategies to optimize {hardware} utilization and environment friendly transaction flows. Verification challenges for system integrators and verification engineers augmented considerably with the appearance of those complicated interfaces.

Cadence, a pacesetter within the verification area, pilots much-needed system-level options to ease bring-up, testing and debug effort and reduce verification cycles for system integrators. This answer is named ‘System Verification IP,’ which incorporates System Visitors Libraries, System Testbench Generator, System Verification Scoreboard, and System Efficiency Analyzer. On this weblog, we’ll discuss in regards to the system verification scoreboard (SVD) and system efficiency analyzer (SPA) taking an actual life instance of workload submission from CHI interface to CXL nodes by way of ARM CMN700 interconnect.

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