ARM Architecture

Avery Design Programs PCI Specific VIP Permits eTopus SerDes IP and Subsequent-Era ASIC and Chiplet purposes to Obtain Compliance and Excessive-Pace Connectivity

Tewksbury, MA., June 21, 2022 — Avery Design Programs, a frontrunner in purposeful verification options, at the moment introduced it has been chosen by eTopus as its verification IP resolution associate for eTopus PCIe Gen 1-6 and 800G/400G Ethernet options and 112G SerDes IP for next-generation ASIC and Chiplet purposes.

eTopus designs ultra-high pace mixed-signal semiconductor options for high-performance computing and information heart purposes. Its excessive pace, low latency, low energy connectivity IP helps modern PCIe and Ethernet connectivity and makes use of Avery’s PCI Specific Verification IP (VIP) to make sure its IP is compliant previous to silicon validation.

“As designs transfer in the direction of increased speeds, ultra-high pace SerDes IP is crucial for vanguard networking, storage, 5G, and AI purposes, mentioned Harry Chan CEO of eTopus. “Avery VIP provides us confidence that our improvements in ADC/DSP-based bodily layer transceiver know-how ship superior bit error fee efficiency, decrease latency and low energy consumption whereas assembly requirements compliance.”

Avery VIP was used to validate the eTopus 7/6nm modular SerDes IP optimized for PCIe gen 1 to six and 800G SoC & Chiplet shoppers. This new 800G resolution helps Ethernet requirements from 1G to 112G with assist for as much as 45+ dB lengthy attain purposes.

The Avery PCI Specific VIP is a complete verification resolution that includes a complicated UVM setting that helps the newest options and capabilities within the high-speed interconnect protocol.

“We’re happy to collaborate with eTopus on the introduction of PCIe Gen6 PHY options to our mutual clients,” mentioned Chris Browy, VP Gross sales/Advertising of Avery Design Programs.

Avery is a frontrunner in PCIe VIP and works with its ecosystem companions to make sure a complete and modern IP resolution. The Avery SystemVerilog/UVM VIP resolution contains fashions, protocol checking, compliance testsuites, and Digital Host QEMU co-simulation – enabling clients to deal with new PCIe 6.0 design and verification challenges even when no mainstream business platforms assist the newest requirements.

About eTopus Expertise Inc.

eTopus is an innovator and know-how chief in excessive efficiency, DSP-based, mixed-signal, ultra-high-speed semiconductor interconnect options. Our ultra-high-speed SerDes IP is adopted by international Tier-1 gamers for use in networking, storage, 5G, and AI purposes. eTopus is a VC-backed startup headquartered within the heart of Silicon Valley the place our improvements and superior architectures are developed. A number of areas are arrange globally in USA, Europe and Higher China to offer gross sales, design and buyer assist. Our traders embrace SK Telecom, HK-X, company VCs, and cross-border funds. For extra info, please go to

Avery Design Programs

Based in 1999, Avery Design Programs, Inc. permits system and SOC design groups to realize dramatic purposeful verification productiveness enhancements by way of the usage of formal evaluation purposes for gate-level X-pessimism verification and actual X root trigger and sequential again tracing; and sturdy core-through-chip-level Verification IP for PCI Specific, CXL, CCIX, Gen-Z, USB, AMBA, UFS, MIPI CSI/DSI, I3C, DDR/LPDDR, HBM, ONFI/Toggle/NOR, NVM Specific, SATA, AHCI, SAS, eMMC, SD/SDIO, CAN FD, and FlexRay requirements. The corporate has established quite a few Avery Design VIP associate program affiliations with main IP suppliers. Extra info is out there at

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