ARM Architecture

Bettering RISC-V Processor High quality with Verification Requirements and Superior Methodologies


On the RISC-V Summit in December, there have been shows midway between a keynote and a technical session. generally known as RISC-V Spotlights. These have been offered to the complete group of attendees however weren’t blessed with the keynote title. Perhaps that is like the way in which that when a doctor in Britain turns into a surgeon, they drop the title “Dr.” and return to “Mr.”. A highlight is even higher than a keynote. One highlight was by Simon Davidmann of Imperas titled Bettering RISC-V Processor High quality with Verification Requirements and Superior Verification Methodologies.

Simon and I am going again a great distance, ever since he was the VP of Gross sales for Ambit in Europe within the period after I was VP of Engineering. Certainly one of our lead prospects was Ericsson in Stockholm, and I keep in mind collectively visiting the group there not less than as soon as. Ericsson was what I regarded as a dream buyer, not less than partially as a result of everybody is aware of who they’re. They have been additionally a dream buyer in one other method: their design was too large for another synthesis software to deal with, however our BuildGates product might simply synthesize the complete design. When that occurs to a buyer, they beautiful a lot would simply say, “please take our cash,” and Ericsson did. However I digress.

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