Grenoble, France — November 24, 2022 — Defacto Applied sciences proclaims that impartial compliance agency SGS-TÜV has licensed the compliance of Defacto’s SoC Compiler 9.0. instrument and documentation and deemed to be match to be used as much as ASIL D automotive design initiatives. Defacto’s SoC Compiler is delivered with complete enablement documentation offering descriptions and finest practices data.
Defacto’s SoC Compiler is an entire SoC integration platform multidimensional and pre-synthesis with a excessive degree of automation taking into account all design data, together with RTL, IP-XACT, timing constraints, energy, bodily, and check.
Earlier than logic synthesis, SoC Compiler allows full implementation capabilities in the direction of IP and connectivity insertion, design enhancing, and views era with real-time monitoring of the combination progress.
Silicon-proven for nearly twenty years, Defacto’s SoC Compiler is each day utilized by main semiconductor firms for giant sorts of purposes equivalent to HPC, cell, VR, AI, and extra.
“Have the ability to present our prospects an IP & SoC design answer for automotive purposes was a should. We’re completely happy and glad at present to present the chance to our prospects to make use of Defacto’s SoC Compiler with confidence for practical security flows” Stated Chouki Aktouf, CEO and Founding father of Defacto.
About Defacto’s SoC Compiler
By way of a unified database with totally different APIs, Defacto’s SoC Compiler allows an economical SoC Construct & Signoff design course of which opens new SoC integration and design optimization capabilities earlier than and after logic synthesis
SoC Compiler helps to face challenges of managing collectively RTL and design collaterals throughout the SoC Design Meeting earlier than logic synthesis together with:
- Energy intent equivalent to UPF
- Timing constraints equivalent to SDC
- Bodily design data equivalent to LEF/DEF
- Architectural design codecs equivalent to IPXACT
- Design Libraries equivalent to Liberty
Additionally, SoC Compiler offers a full automation to generate prepared for RTL to GDS circulation: RTL, UPF and SDC recordsdata by contemplating bodily, energy, timing & DFT constraints.
About Defacto Applied sciences
Defacto Applied sciences is a chip design software program firm offering breakthrough System on Chip design options to reinforce design integration, design verification, and in addition the Signoff of IP cores, subsystems, and huge SoCs.
By adopting Defacto’s SoC Compiler design options, main semiconductor firms are constantly transferring from conventional and painful SoC design duties to Defacto’s joint “Construct & Signoff” design methodology. The associated ROI has been confirmed for a whole lot of initiatives.
Headquartered within the French Alps with a US department in California, Defacto has at present a worldwide presence with 24/7 assist all around the world.
Defacto’s EDA instruments beforehand named STAR have gained maturity for twenty years not as standalone instruments however as a joint answer within the technique of constructing massive SoCs.
In 2021, Defacto’s main Launch 9.0 completes the method of constructing in front-end an SoC from both scratch and/or ranging from present initiatives
Consequently, it turns into a mature SoC design answer that takes person specification together with constructing blocks and robotically generates SoC RTL & collaterals, prepared for logic synthesis.
For extra details about our answer Defacto’s SoC Compiler, be at liberty to test our web site: https://defactotech.com/ or to contact us immediately at firstname.lastname@example.org . We shall be more than pleased to reply your questions and assist serve your wants the very best.
We sit up for working with you on automotive and practical security purposes!