Excessive-end SOC architectures as we speak requiring extra space and better velocity to switch and course of information. To satisfy this requirement, protocol resembling PCIe, USB, DP, SATA and USB4 are frequently being up to date. Most crucial a part of the high-speed interface is the Bodily (PHY) layer of the protocol the place the precise signaling occurs. Along with signaling, the PHY additionally takes care of a number of the processing to cut back errors in transmission and error restoration. This makes the PHY design very advanced because it entails each excessive velocity digital logic and analog circuitry. Often the remainder of the protocol could be applied purely utilizing digital logic. Therefore the IP/SoC builders develop the PHY individually from the remainder of the protocol logic. This can enable each developments to occur in parallel and independently. This created a necessity for the standard interface between PHY module and remainder of the protocol logic. The PIPE specification successfully defines this interface. One of many intents of the PIPE specification is to speed up the event of PCIe, SATA, USB, USB4, DP MAC. The latest adjustments within the PIPE is SerDes structure and low pin depend interface. The PIPE specification has upgraded to model 6.1.1 to match the newest protocol specs of PCIe, DP and USB4.