ARM Architecture

Mitigating Digital Logic Comfortable Errors within the Terrestrial Surroundings


By Synopsys

As expertise scales, gentle errors from particle radiation have gotten more and more regarding for in-field reliability. These radiation results are referred to as Single Occasion Upsets (SEU) and the frequency of the failures attributable to SEUs is called the Comfortable Error Fee (SER). Comfortable errors are failures attributable to exterior sources. Against this, laborious errors discuss with precise course of manufacturing defects or electromigration defects that get shaped throughout circuit operation. Exhausting errors can’t be fastened with out altering the silicon; gentle errors are often momentary, and the circuit subsequently returns to performance.

In older applied sciences, this SEU drawback was restricted to radiation-hostile environments reminiscent of house. With applied sciences scaling to smaller geometries, and with the elevated variety of components built-in right into a system-on-chip (SoC), each part in an SoC is now inclined to particle radiation. Subsequently, the SoC total has a better chance of affected by SEUs. Of the varied SoC parts, SRAMs and standard-cell sequential components might expertise knowledge upset. Equally, combinational circuits might expertise gentle delay errors or glitches which can influence the timing and/or performance of the SoC and finally trigger knowledge failure. This interprets into the potential for a better SER for smaller geometry SoCs, and this impact must be thought-about in designs for high-reliability purposes like Automotive, Datacenter & Excessive-Efficiency Computing.

On this paper, we are going to:

  • Assessment the forms of radiation particles and the sources of radiation that influence circuit SER
  • Tackle the strategies to mitigate terrestrial radiation influence in SoC design for high-reliability purposes reminiscent of Automotive and Datacenter
  • Talk about the influence of expertise scaling from planar to FinFET on SoC reliability because of the SER impact
  • Describe how Synopsys logic libraries are SEU-optimized whereas nonetheless assembly the stringent energy, efficiency, and space (PPA) necessities of FinFET SoCs

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