ARM Architecture

NXP LPC17xx/40xx: Decoding the Half ID


That is the primary weblog of a quantity coping with the NXP LPC17xx/40xx processor households and methods to program them regardless of the dearth of documentation.  The subsequent weblog will take care of implementing the LPC17xx/40xx UART with interrupts correctly, and a subsequent weblog will present methods to use the UART in RS485 Regular Multidrop Mode (NMM) with Auto Handle Detection (AAD).

My firm has selected utilizing the NXP LPC17xx/40xx processor line for all our embedded tasks.  Since every processor within the line is similar to the opposite processors, I wrote a {hardware} layer that may deal with all processors.  The variations are dealt with by studying the half ID to find out which processor/household the applying is operating on.  However it began getting very costly flash-wise once I began making tables exhibiting how a lot reminiscence every processor contained, if it may deal with 120 MHz or not, and so on.

It was about this time I began taking have a look at the half ID desk values, particularly the desk for the LPC177x/8x proven right here:

The half IDs did not make a lot sense.  Why not simply give them the values of 1774 to 1788?  Then I noticed that they have been flags that confirmed the capabilities of the processor.  So I sat down with the varied manuals and began decoding the flags.  After about an hour, I ended up with a set of #defines that masked out bitfields or outlined bits denoting the capabilities of the processor.

The half ID is learn by calling into the NXP boot code at deal with 0x1FFF1FF1 utilizing the In Utility Programming (IAP) command 54.  See the Flash Reminiscence chapter in every processor consumer handbook for extra data on methods to make the decision.  One factor not talked about within the documentation is that you have to disable interrupts as a result of the exception vector desk at deal with 0 could also be remapped throughout the name.

NXP LPC17xx/40xx processor line is available in two households with 4 teams in every household.  The processor households are LPC17xx and LPC40xx, and the teams are LPCxx5x, LPCxx6x, LPCxx7x, and LPCxx8x.

The next are the definitions I exploit to extract the varied bit fields and flags.  To extract a bit area, shift the half ID proper by the shift worth after which apply the masks.  To verify a bit, AND it with the half ID and verify for nonzero.

#outline Bit(BitNum)     (1u << (BitNum))

#outline NXP_FAMILY_SHIFT        28      //!< Household proper shift worth
#outline NXP_FAMILY_MASK         0x0Fu   //!< Household masks
#outline NXP_FAMILY_LPC17xx      0x02u   //!< LPC17xx household
#outline NXP_FAMILY_LPC40xx      0x04u   //!< LPC40xx household

#outline NXP_GROUP_SHIFT         24      //!< Group proper shift worth
#outline NXP_GROUP_MASK          0x0Fu   //!< Group masks
#outline NXP_GROUP_LPCxx5x       0x05u   //!< LPCxx5x group
#outline NXP_GROUP_LPCxx6x       0x06u   //!< LPCxx6x group
#outline NXP_GROUP_LPCxx7x       0x07u   //!< LPCxx7x group
#outline NXP_GROUP_LPCxx8x       0x08u   //!< LPCxx8x group

#outline NXP_120_MHZ          (1u << 20) //!< 120 MHz succesful
#outline NXP_SD_CARD          (1u << 19) //!< SD card
#outline NXP_LCD              (1u << 18) //!< LCD
#outline NXP_PRAM             (1u << 16) //!< Peripheral reminiscence (PRAM) accessible
#outline NXP_PRAM_32K         (1u << 13) //!< 32K peripheral reminiscence
#outline NXP_CAN              (1u << 12) //!< CAN bus
#outline NXP_ETHERNET         (1u << 11) //!< Ethernet
#outline NXP_USB_OTG          (1u << 10) //!< USB On-The-Go
#outline NXP_USB_HOST         (1u <<  9) //!< USB host
#outline NXP_USB              (1u <<  8) //!< USB

#outline NXP_RAM_SHIFT           4       //!< RAM measurement proper shift worth
#outline NXP_RAM_MASK            0x0Fu   //!< RAM measurement masks
#outline NXP_RAM_8K              0x01u   //!< 8 KB RAM
#outline NXP_RAM_16K             0x02u   //!< 16 KB RAM
#outline NXP_RAM_32K             0x03u   //!< 32 KB RAM
#outline NXP_RAM_64K             0x04u   //!< 64 KB RAM

#outline NXP_LPC1751_CRP      (1u <<  3) //!< CRP (LPC1751 solely, else all the time 0)

#outline NXP_FLASH_SHIFT         0       //!< Flash measurement proper shift worth
#outline NXP_FLASH_MASK          0x07u   //!< Flash measurement masks
#outline NXP_FLASH_32K           0x00u   //!< 32 KB flash
#outline NXP_FLASH_64K           0x01u   //!< 64 KB flash
#outline NXP_FLASH_128K          0x02u   //!< 128 KB flash
#outline NXP_FLASH_256K          0x03u   //!< 256 KB flash
#outline NXP_FLASH_512K          0x07u   //!< 512 KB flash

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