ARM Architecture

Remoted Sigma-Delta Modulators, Rah Rah Rah!


I not too long ago confronted a bit of “asterisk” downside, which seems like it may be solved with some attention-grabbing ICs. 

I wanted to plan out some take a look at instrumentation to seize voltage and present info over a brief time period. Nothing too fancy, 10 or 20kHz sampling charge, a few half-dozen channels sampled concurrently or close to concurrently, for perhaps 5 or 10 seconds.

This is the “asterisk”: Oh, by the best way, as a result of the system in query was tied to the AC mains, I wanted some voltage isolation.

With out isolation, a working answer would in all probability price within the $200-$450 vary. With isolation it in all probability pushes the price an order of magnitude to $2000-$4500. There’s all the time the potential of pushing the isolation on the opposite aspect of the ADC: as an alternative of analog isolation, utilizing a non-isolated USB information acquisition system with an remoted USB adapter; that provides $50-$150 additional in price… however all of the alerts in query must be referenced to about the identical potential, and so they aren’t on this case.

Analog isolation is a ache. There aren’t many choices; you should use considered one of these dual-feedback optoisolator modules just like the Avago HCNR201 or the modulation/demodulation model just like the TI ISO124.

Whereas searching for an answer, I ran throughout a handful of ICs from just a few producers that seem like they could do the trick. These are sigma-delta modulators (typically known as delta-sigma modulators):

These are remarkably comparable in specs, and I am undecided who got here out with the primary of those chips (in all probability Agilent with the HCPL-7560 earlier than they spun off the previous Hewlett-Packard optoelectronics division into Avago; since then Avago has modified the half numbering from HCPL to ACPL). You stick an analog 5V energy provide on the remoted aspect, alongside together with your enter sign, and on the opposite aspect you energy the IC and get an information stream output, together with both a clock restoration output or a clock enter. From the point of view of designing them right into a high-volume product, they’re type of costly (in comparison with less complicated ADCs which use successive approximation registers), at $3-$5 every in massive portions; for take a look at instrumentation, at $6-$10 every in small portions, they’re quite a bit inexpensive than different options.

So what’s a sigma-delta modulator?

Sigma-delta: the ability of avoiding the “I Need It Now” strategy to ADC

You’ve got in all probability heard of sigma-delta analog-to-digital converters. These have been round for some time, particularly within the above-16-bit marketplace for ADCs. Traditionally they had been used for very sluggish however very exact measurements: the basic software is pressure gage digitization for weigh scales. Now you should buy 24-bit ADCs from a number of producers and so they have built-in 50/60Hz notch rejection.

Not like the Successive Approximation Register (SAR) and Flash varieties of ADCs, each of which have sample-and-hold inputs (the “I need it now!” strategy), sigma-delta converters do issues a bit of otherwise. These converters have two components (no, they are not “sigma” and “delta”):

  • a modulator, which takes an analog voltage and creates a quick stream of low-resolution (often 1-bit) ADC samples to oversample the enter waveform
  • a filter, which takes the quick low-resolution ADC samples, and filters and decimates them to generate a decrease pace stream of high-resolution ADC samples.

The standalone ADCs do all this for you; you simply deal with them like a SPI peripheral to arrange management registers and skim again the high-resolution ADC information.

I would not be capable of do justice to explaining the best way these work intimately; for that, I might advocate quite a few references (see the top of this weblog article) however particularly the MT022 tutorial on sigma-delta conversion from the legendary Analog Gadgets engineer Walt Kester, who has been at ADI since 1969.

This is the essence of the concept: Analog-to-digital conversion will be seen as conversion of a continuously-varying sign to at least one that has discrete ranges, and this course of will be considered as including quantization “noise” (the distinction between the continual enter and the discrete-leveled output). Sigma-delta conversion pushes this noise “away” from the sign by each oversampling, the place the quantization noise smears out over a bigger spectrum, and “noise shaping”, which biases the noise into the high-frequency portion of the info and retains it largely out of the low-frequency portion of the info — which is the place the sign you care about resides. Then the filtering a part of the sigma-delta converter can take away the majority of the quantization noise.

(Figures from Analog Gadgets MT-022.)

To do the noise shaping, it takes a sigma-delta modulator. This is what a second-order sigma-delta modulator seems like:

If you wish to know the way it works to trigger noise shaping, you will need to learn among the references intimately and get into frequency-domain evaluation and what-not.

The important thing options of a sigma-delta modulator are this:

  • It is a 1-bit ADC which is basically quick and actually correct at low frequencies in comparison with the clock charge. (That’s — you do not have a look at every particular person little bit of the output, you have a look at the bitstream and study the density of 1s through low-pass-filtering.)
  • It is an integrating converter — you do not pattern the enter at a selected on the spot; as an alternative the enter voltage repeatedly has an impact on the digitization.
  • You get enhanced efficient bit accuracy for oversampling. For a “common” ADC, every time you double the pattern charge and common the outcomes, you get one other 1/2 little bit of efficient decision. (For twice the decision you want 4x the pattern charge.) With a 1st-order sigma-delta modulator, due to the noise shaping, in case you double the pattern charge, you get one other 3/2 bits of efficient decision. (For twice the decision you solely want to extend sampling frequency by an element of two(2/3) = 1.59) With a 2nd-order sigma-modulator, in case you double the pattern charge, you get one other 5/2 bits of efficient decision. (For twice the decision you solely want to extend sampling frequency by an element of two(2/5) = 1.32)

Right here we get to the great components.

With a sampling ADC, you need to resolve when to pattern, and hope that your enter would not have a lot noise round these sampling instants, and that it would not have a lot ripple content material above the Nyquist frequency (half the sampling frequency) the place it could idiot the ADC into giving the incorrect outcomes. With a sigma-delta ADC, you do not actually need to fret about that, for 2 causes: one is that the ADC bit charge is so excessive that you should use a extremely low-cost RC filter to do away with ultra-high frequency content material, and the opposite is that even when some high-frequency noise will get via, will probably be averaged out by the enter integrator.

And if the sigma-delta clock charge is synchronized to a a number of of one other system supply, like a PWM sign or a present waveform with ripple on the PWM frequency, then you’ll be able to do away with this ripple altogether and skim simply the typical worth of the enter. Which is nice for energy electronics.

That is the great a part of the integrator. The truth that it is a 1-bit ADC which places out a stream of digital bits, means we solely want 1 digital isolation channel if we need to get the ADC throughout an isolation barrier, together with a 2nd channel for clock enter or clock restoration, and we needn’t deal with a SPI protocol (when mixed with an isolation barrier, this implies worrying about bit timing and round-trip latency and all that); the bits simply come alongside and also you cope with them one after the other by one.

Filtering and downsampling

So it is a no-brainer!…. aside from one factor. How do you cope with a 10-20MHz stream of digital bits? I imply, come on, info overload!

Effectively, this is the onerous half, then. Should you’re doing real-time management, that is quick sufficient that you simply’d higher be utilizing a devoted sigma-delta filter/decimator, or be good with FPGA programming. The idea behind filtering and downsampling is definitely fairly simple. Numerous functions use Third-order sinc filters, also called cascaded integrator-comb filters. These are nice for digital functions. There is not any multiplies concerned, simply provides, subtracts, and single-step delays.

You principally do that on the enter aspect, at a quick charge:

sum1 += enter
sum2 += sum1
sum3 += sum2

after which on the output aspect at a submultiple of the quick charge, each N iterations:

diff3 = sum3 - sum3_prev
sum3_prev = sum3
diff2 = diff3 - diff3_prev
diff3_prev = diff3
output = diff2 - diff2_prev
diff2_prev = diff2

This provides you a low-pass filtering together with a decimation robotically, and a scaling issue of Nok the place ok is the variety of sections within the comb filter. (3 within the above instance.)

What I do want, is that there have been some information acquisition methods that took in sigma-delta bitstreams and dealt with the filtering/decimation and bought the outcomes into reminiscence in your PC. Sigma-delta ADCs are good, but it surely’s way more highly effective (and provides you the power to make use of easy 1-bit digital isolation) when you should use a sigma-delta modulator and mix it with a separate filter/decimator that permits you to select what clock to make use of, how briskly to oversample it, and many others.

In any case, issues have been bettering over time, and I look ahead to at some point with the ability to use sigma-delta converters not just for instrumentation, however for embedded management as properly.

Glad changing! 

References:

MT-022 ADC Architectures III: Sigma-Delta ADC Fundamentals — Walt Kester, Analog Gadgets

MT-023 ADC Architectures IV: Sigma-Delta ADC Superior Ideas and Purposes — Walt Kester, Analog Gadgets

How delta-sigma ADCs work, half 1 — Bonnie Baker, Texas Devices

How delta-sigma ADCs work, half 2 — Bonnie Baker, Texas Devices


p.s. I have not forgotten concerning the second a part of Estimate Encoder Velocity With out Making Silly Errors, which can cowl PLLs and observers; my life has been actually busy these days, and to do that subject justice I in all probability will not get sufficient time to complete it till later this yr. Keep tuned!

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