ARM Architecture

RISC-V CEO Calista Redmond and Maven Silicon CEO Sivakumar P R on RISC-V Open Period of Computing


India’s high VLSI Coaching Companies firm Maven Silicon, a RISC-V International Coaching Associate, carried out an insightful dialogue with the business consultants Ms. Calista Redmond, CEO, RISC-V Worldwide and Mr. Sivakumar P R, CEO, Maven Silicon, on the subject “RISC-V Open Period of Computing”.

To introduce RISC-V, it’s a free and open ISA, enabling processor, {hardware}, and software program improvements by open collaboration.

Maven Silicon’s imaginative and prescient is to supply extremely expert VLSI engineers and assist the worldwide semiconductor business to achieve skillful chip design consultants. The worldwide semiconductor business is remodeling quicker than ever, enabling us to create highly effective built-in chips to strengthen the following technology of advancing applied sciences like IoT, AI, Cloud, and 5G. So, we have to produce expert chip designers who can design extra highly effective and optimized processors of various varieties. That is how we intention to disrupt the semiconductor business. Our imaginative and prescient aligns with that of RISC-V’s in disrupting the semiconductor business.

We’re delighted to introduce our Business experts who honored the dialogue.

  1. Ms. Calista Redmond, CEO, RISC-V Worldwide
    Calista Redmond, CEO of RISC-V Worldwide has greater than 20 years of senior-level administration and alliance expertise, together with important open supply neighborhood expertise. All through her profession, she has developed strategic relationships with the chip, {hardware}, and software program suppliers, system integrators, enterprise companions, shoppers, and builders.
  2. Mr. Sivakumar P R, ​Founder and CEO, Maven Silicon
    Sivakumar is the Founder and CEO of Maven Silicon. He’s additionally the Founder and CEO of Aceic Design Applied sciences. He’s a seasoned engineering skilled who has labored in varied fields, together with electrical engineering, lecturers, and the semiconductor business for greater than 20 years and makes a speciality of providing Verification IPs and consulting companies and EDA stream improvement.

This profound ‘Skilled speak’ was hosted by Ms. Sweety Dharamdasani, Head of Studying & Improvement Division at Maven Silicon, who’s extraordinarily obsessed with upskilling the younger aspirants.

The dialogue highlighted some unimaginable matters on RISC-V, and the way it may be leveraged in redefining the VLSI curriculum.

Sweety: I want to perceive from Calista the What and Why of RISC-V? An introduction for our viewers on RISC V, please.

Calista: Alongside the journey of the {Hardware} business, RISC-V found the collaboration in software program that helps your entire business to type a basis upon which they will nonetheless compete. Now, there’s a growth in custom-made processors, and they also have taken on the chance.

Beneath are the 2 explanation why RISC-V catapulted to being probably the most prolific open ISA that the microprocessor business has ever seen:

  • Disruptive expertise
  • Design Flexibility with unconstrained alternatives

Sweety: Why RISC V? What have been our causes for collaboration with RISC V?

Siva: RISC-V is an open ISA. It’s free, no license constraints, however nothing comes totally free in the case of designing the chip. Nonetheless RISC-V is particular due to the liberty we engineers take pleasure in in designing the processor as we like. Additionally, we want specialised processors to construct the chips as monolithic semiconductor scaling is failing. As RISC-V is an open and free ISA, it empowers us to create totally different varieties of specialised processors.

Why RISC-V for Maven: VLSI engineers want to grasp how we construct digital techniques like laptops/smartphones utilizing chips and SoCs. Clearly, we want processors to construct any chips/SoCs. With out understanding the processor, the VLSI engineers can’t cope with any sub-systems/chips. VLSI coaching has at all times been about coaching engineers on totally different languages, methodologies, and EDA level instruments. So, we launched processors as a part of our VLSI course curriculum to redefine the VLSI coaching. As RISC-V is open, easy, and modular ISA, it was our alternative.

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Sweety: So what is going on within the RISC V area proper now? If you need to share some success tales or developments, it will be nice.

Calista: The predictions say that the semiconductor IP market will go from 5.2 billion {dollars} in 2020 to eight.6 billion {dollars} in 2025. We’re on the right track with the prediction that RISC-V will devour 28% of that market in IoT, 12% in industrial, and 10% in automotive. Many enterprise capitalists are investing billions of {dollars} in RISC-V corporations. There are lots of alternatives right here for many who are beginning their very own corporations and plenty of extra success tales are popping out day-after-day.

Sweety: What are our present plans which can be occurring with RISC-V?

Siva: We’re doing many issues creatively with RISC-V. We’ve included RISC-V in our VLSI course curriculum, and it’s open to all new school graduates, engineers, and even company companions.

Since Jan 2022, we have now skilled greater than 200+ engineers in varied domains, RTL Design, Verification and DFT, for a world chipmaker. All of them have used RISC-V/RISC-V SoCs as their initiatives/case research to be taught all these totally different applied sciences. It really works fantastically.

Since we turned RISC-V world coaching accomplice, we skilled 1000+ engineers on RISC-V processor design and verification and launched them to our semiconductor ecosystem.

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Sweety: What are we by way of the long run for RISC V?

Calista: Being profitable within the microprocessors or in any enterprise with some small incremental development won’t be useful. What we do in RISC-V is unimaginable. We’ve 12000 builders who’re engaged with RISC-V. We’ve 60 totally different technical works which have been occurring, which has been an unimaginable praise for the training and the knowledge-based group like Maven Silicon.

Sweety: What are our plans at Maven Silicon with regard to RISC V? Any upgrades on curriculums?

Siva: New functions will demand RV128. There can be new safety challenges, however nonetheless RISC-V will emerge as an business normal open ISA for every kind of specialised processors, changing many of the present proprietary ISAs.

At Maven, we might be including extra new matters like advanced pipelining, floating level core design, cache controllers, low energy mode, compilers, and debuggers, and so forth., into our present RISC-V course curriculum. We’re additionally wanting ahead to creating long-term grasp studying packages like designing SoC utilizing RISC-V.

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Sweety: It might be nice when you can share with us a number of ideas for all our younger VLSI aspirants, who plan to construct a profession within the semiconductor business.

Calista: Perceive the place your capacity matches within the VLSI area. Join along with your mentors, colleagues, friends, and co-work shoulder to shoulder, and strengthen your community in your area. If you work collectively, you be taught quicker and perceive higher. You may choose any of the 60 programs that we have now and be a part of RISC-V and be taught the matters which can be occurring within the varied areas within the RISC-V area.

Sweety: What are the few ideas that you simply want to share with the younger engineers?

Siva: One main piece of recommendation I want to give to the following technology is that “Don’t select the area based mostly on the recognition, select no matter you have an interest in. Don’t lose motivation when issues don’t fall in place, simply do it sincerely”. Search steerage from the individuals who will enable you to to develop higher. Studying is a steady course of, ask inquiries to your self and continue learning. Be a part of a Non-profit group like RISC-V that’s contributing to the engineering neighborhood.

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Sweety: What are your takes on organizational tradition, sensitivity, gender consciousness, ladies in enterprise, and so forth?

Calista: It is very important drive ourselves as ladies, and all of us to create an atmosphere and alternatives to domesticate the ladies round us. It’s tough to be within the highlight as it’s extra clear, however you will need to take these steps. Discover out the eagerness that can drive us. It is very important work in an organization that you simply consider in and to develop with them. Elevate up the folks round you. Shine the sunshine on others to assist domesticate their success, whereas cultivating your personal.

Sweety: We all know that Maven Silicon voices out to folks. Round 60% of our workers are ladies. How do you maintain your workers?

Siva: I want to point out right here our Co-founder and Managing Director Ms. Praveena G who’s all about folks and processes. She is extraordinarily composed, trustworthy, and detail-oriented whereas I have a look at the large image and do enterprise creatively. Together with our co-founder there are various tremendous gifted ladies who do wonderful issues at Maven and assist us keep on the high of our recreation.

Organizational tradition displays the fashion of management. Our tradition relies on our core values. We respect our prospects, companions, and workers. We consider in ‘Lead with out Title’.

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We really respect Ms. Calista Redmond and Mr. Sivakumar P R for sharing their experiences, and so fantastically explaining the varied matters together with RISC-V, ideas for the younger aspirants, ladies empowerment, and the organizational tradition. Additionally, we want to thank RISC-V Worldwide for this nice alternative to work with their open-source neighborhood and contribute to RISC-V studying as a RISC-V International Coaching Associate.

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