ARM Architecture

VHDL tutorial – A sensible instance – half 1 – {Hardware}


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In earlier posts I described some easy VHDL examples.  This time let’s attempt one thing somewhat extra advanced. That is half considered one of a a number of half article.  That is supposed to be an in depth description of considered one of a number of preliminary designs that I developed for a shopper.  This design by no means made it right into a product, however an identical design was used and is at the moment being produced.  As a substantial quantity of labor was put into this effort, I made a decision to share this design by means of this discussion board versus burying it fully. This design was supposed to be an information acquisition sub-system for a low energy, handheld instrument. 

This half focuses on the {hardware} design, together with a number of the VHDL definitions of the I/O traits of the CPLD half.  Future entries will describe the VHDL logic of the CPLD, together with the simulations of the half. 

As acknowledged above, the ultimate design ended up trying fairly completely different, however this specific design was fairly fascinating to me, because it achieved the acknowledged necessities, but additionally supplied some further performance that was a pleasant bonus.  Earlier than I get too far forward of myself, let’s take a look at the fundamental necessities.

The entire design for this instrument contained a number of sections, however my half was the information acquisition logic.  On one facet there was a small μProcessor, which dealt with the keypad, LCD and different elements of the consumer interface.  This μProcessor can be interacting with my design and can be answerable for crunching the numbers on the information captured by the acquisition logic. On the opposite facet there was a laser driver (with programmable excessive and low present settings) and a pair of photodiodes and related preamps.  In center, was my half, the information acquisition engine.

The information acquisition engine has the next primary capabilities:

1) Present for synchronous (with sampling, under) switching of the Laser diode between the excessive and low output ranges (managed by a twin channel ADC, programmed by the μProcessor utilizing SPI) at an approximate charge of about 2 KHz.

2) Acquire a burst of information, made up of packets of 16 evenly spaced samples, of 16 bits per channel (2) for every cycle of the Laser diode, for about 1 second.

3) Permit for numerous pattern lengths ( ~1 sec, ~0.5 sec, and so forth.).

4) Sign the μProcessor with an ‘finish of assortment’ interrupt.

Along with the above capabilities, the circuit wanted to devour as little energy as doable, as this was to be a battery powered gadget.  Throughout information assortment, present attracts of 20-40mA was accceptable. Throughout idle operation, present draw ought to be much less the 1mA (the decrease the higher).

Numerous approaches have been thought of, however in the long run, it was determined to gather the samples regionally right into a SRAM gadget, then interrupt the μProcessor on the finish of the cycle and permit the μProcessor to obtain the information and course of as obligatory.  This is able to require about 128K bytes of storage, storing at a charge of ~ 1M bit/sec.

Along with the above necessities, there was a necessity to reduce the interface to the μProcessor, as a lot of the pins have been devoted to different capabilities.  Given this limitation the next interface to the μProcessor was outlined:

  • Mclk – Grasp Clock, 8MHz clock
  • Reset – Lively Low
  • SCLK, SDI & SDO – SPI bus alerts
  • CS1 & CS0 – Chip choose decode alerts (to CPLD, ADC and  serial SRAM)
  • Int – Interrupt line to sign course of full (energetic excessive)

Of those alerts, solely Mclk, CS1, CS0 and Int are distinctive.  The SPI bus traces and Reset have been already assigned to work with different parts of the circuit.  So, solely 4 further pins have been required to offer an interface to the acquisition circuit.  The Mclk sign (8MHz) was to be switchable, in order that the information acquisition logic would go right into a deep sleep (very low present draw) when not use. 

The VHDL definitions for these alerts are described as follows:

One of many compelling elements of the {hardware} strategy for this design, was the distinctive purposes of some fascinating elements.  For this design I discovered some comparatively low-power elements, that I do not usually use in my designs, together with a few of my common favorites (XILINX CPLDs).  The next is a brief description of the most important part within the design.

  • ADC – PCM1870 – 16-bit, low energy stereo audio ADC.  This gadget is utilized in many industrial gadgets, together with transportable audio gamers/recorders and mobile telephones.  Designed for audio, it supplies sampling as much as 50KHz, whereas offering a number of programmable options like: 30 db to -12 db acquire, three-band tone management and high-pass and notch filtering.  These have been very compelling capabilities given issues in earlier designs of comparable product with noise points attributable to excessive energy switching (laser) subsequent to low stage inputs (photodiodes).  This gadget is managed by the SPI bus (by the μProcessor by way of the CPLD) and sends out transformed information by way of the I2S (Inter-IC Sound, Built-in Interchip Sound) bus, which is relayed to the SRAM (by way of the CPLD).
  • SRAM – CY14B101Q2 – 1 MBit (128K x 8) serial SPI nvSRAM.  This gadget acts a quick SRAM throughout information assortment, but additionally supplies a non-volatile storage utilizing Quantum Entice parts (underneath program management or on energy fail).  The SPI timing for this components runs as much as 40MHz, offering write cycles of < 200 ns.  The added non-volatile storage, whereas not wanted for storing sensor studying, might be used for storing gadget setup and calibration information (good added bonus). This gadget shall be written to by the SPI bus (underneath command of the CPLD) and browse from the μProcessor (by way of the CPLD)
  • CPLD – XC2C64A – 64-macrocell, low-power, low-cost CPLD.  That is considered one of my favourite components, one which I’ve constructed a number of gadgets round.  Small and quick, the pliability of those components is the explanation that I preserve coming again to them. This gadget shall be programmed to perform as an SPI bus peripheral (acquisition run size and run command) and as a SPI repeater (passing information to/from the ADC and SRAM).  This gadget can even generate the entire obligatory clocking and management traces (SPI and I2S) to run the acquisition bursts.

Given the most important elements, it’s essential to outline the sign circulation between the items.  Because the CPLD is performing as a SPI bus repeater (and sequencer) we’ll want one other set of I/O pins for the inner (ADC/SRAM) SPI bus.  This may embody SCLK, SDI & SDO in addition to chip selects for the ADC and the SRAM. The VHDL definitions for these alerts are described as follows:

 

The ADC to CPLD interface is achieved by means of the I2S bus.  It requires solely three alerts with a view to clock information from the ADC.  The interface shall be operated within the DSP or Slave mode the place the CPLD will generate the LRCK (Left and Proper clock) and the BCK (Serial bit clock), whereas the ADC will present information by means of the DOUT (Serial audio information output) line. The VHDL definitions for these alerts are described as follows:

The one remaining interface sign for the design is for controlling the Laser present.  This can be a digital sign that toggles the Laser present management between two programmed settings (0 for low energy and 1 for top energy). The VHDL definition for this sign is described as follows:

We’ll get again to the VHDL coding later, however we now have sufficient info to assign pins to the CPLD and generate a schematic physique for the CPLD half which is able to turn out to be a part of our closing design.  Right here is schematic physique for the Knowledge Acquisition Engine CPLD:

Along with the beforehand outlined pins there a sequence of pre-assigned pins which can be wanted to help the chip.  These embody energy alerts VIO1 (3.3V), VIO2 (3.3V), VCC (1.8V) and VAUX (3.3V), floor pins (GND1 GND2 and GND3) and the JTAG programming connections (TDI, TMS, TCK and TDO).  Of the 44 pins on this gadget, there are 16 that stay unassigned (NC_1 to NC_16) based mostly on the present assignments.  This may permit some room for future development, ought to there be remaining macrocells out there after the design is coded and fitted.

The one lose finish at this level within the design is energy.  The general design requires 3.3V energy, so the 1.8V provide, required by the CPLD, should be sub-regulated from the three.3V provide.  For this design, I used a MIC5253-1.8YC5, 100mA, low-noise, LDO regulator from Micrel to produce the 1.8V.  The low quiescent present (75μA) and small footprint made this a very good match to the design.

With all the main points in place we are able to full the schematic diagram for the entire information acquisition sub-system. Indicators to/from the μProcessor are proven on the left hand facet, whereas alerts to/from the Laser/photodiode module are proven on the suitable hand facet.  The finished schematic is proven under:

This beautiful a lot completes the preliminary {hardware} design.  The following steps shall be to design the VHDL code wanted to offer the specified performance.  This shall be coated within the subsequent a part of this text. Hopefully this instance has clearly demonstrated to the viewers a number of the steps wanted to create a design based mostly on advanced programmable logic gadgets (CPLD). 

Thanks for following together with me on this design instance, I sit up for your feedback, questions and options, as I put together the remaining components of this text.

Good luck and comfortable designing!

Gene

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