By Elad Shliselberg, Ronen Hyatt (UnifabriX Ltd.)
ElectronicDesign (August 24, 2022)
Compute Categorical Hyperlink (CXL) is a cache-coherent interconnect, designed to be an industry-open commonplace interface between platform features reminiscent of processors, accelerators, and reminiscence.
CXL 1.1 is the primary productized model of CXL. It brings ahead a world of potentialities and alternatives to enhance upon the various sturdy options that exist within the PCI Categorical (PCIe) arsenal. The specification introduces the idea of reminiscence growth, coherent co-processing by way of accelerator cache, and device-host reminiscence sharing.
The wealthy set of CXL semantics goes a lot past the acquainted cxl.io (PCIe with enhancements) to additionally provide cxl.cache, and cxl.mem. These semantics are teams into System Varieties: 1 (cxl.io/cxl.cache), 2 (cxl.io/cxl.cache/cxl.mem) and three (cxl.io/cxl.mem).
Given the disruptive nature of CXL, its true worth and potential ecosystem of functions are but to be realized as soon as it’s deployed at scale. As the usual evolves, CXL 2.0 builds upon CXL 1.1 and uncovers new alternatives to additional strengthen the robustness and scalability of the know-how, whereas being absolutely backward appropriate with CXL 1.1.
On this article, we’ll discover the basic capabilities of CXL and spotlight the first variations between CXL 2.0 vs. CXL 1.1, in addition to the enhancements made because the protocol natively evolves.